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8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS77C1000 GMS77C1001
User's Manual (Ver. 1.1)
Version 1.1 Published by MCU Application Team (c)2001 Hynix Semiconductor All right reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS77C1000/GMS77C1001
Contents of Table
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Port RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . 23 I/O Successive Operations . . . . . . . . . . . . . . . 23
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 2 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . 3 PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . 4 PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . 6 PORT STRUCTURES . . . . . . . . . . . . . . . . . 7 ELECTRICAL CHARACTERISTICS . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . 9 Recommended Operating Conditions . . . . . . . 9 DC Characteristics (1) . . . . . . . . . . . . . . . . . . 10 DC Electrical Characteristics (2) . . . . . . . . . . 11 AC Electrical Characteristics (1) . . . . . . . . . . 12 AC Electrical Characteristics (2) . . . . . . . . . . 13 Typical Characteristics . . . . . . . . . . . . . . . . . . 14
TIMER0 MODULE AND TMR0 REGISTER 25
Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . 26 Using Timer0 with an External Clock . . . . . . . 27 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CONFIGURATION AREA . . . . . . . . . . . . . 29 OSCILLATOR CIRCUITS . . . . . . . . . . . . . 30
XT, HF or LF Mode . . . . . . . . . . . . . . . . . . . . 30 RC Oscillation Mode . . . . . . . . . . . . . . . . . . . 30
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 33 Internal Reset Timer (IRT) . . . . . . . . . . . . . . . 35
WATCHDOG TIMER (WDT) . . . . . . . . . . . 36
WDT Period . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WDT Programming Considerations . . . . . . . . 36
ARCHITECTURE . . . . . . . . . . . . . . . . . . . 17
CPU Architecture . . . . . . . . . . . . . . . . . . . . . . 17
MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Memory . . . . . . . . . . . . . . . . . . . . . . 18 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 18 Special Function Registers . . . . . . . . . . . . . . 19
Power-Down Mode (SLEEP) . . . . . . . . . . 37
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Wake-up From SLEEP . . . . . . . . . . . . . . . . . . 38 Minimizing Current Consumption . . . . . . . . . . 38
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . 23
Port RA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD) . . . . . . . . . . . . . 40 POWER FAIL DETECTION PROCESSOR 41
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GMS77C1000 / GMS77C1001
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The GMS77C1000 and GMS77C1001 are an advanced CMOS 8-bit microcontroller with 0.5K/1K words(12-bit) of EPROM. The Hynix Semiconductor GMS77C1000 and GMS77C1001 are a powerful microcontroller which provides a high flexibility and cost effective solution to many small applications. The GMS77C1000 and GMS77C1001 provide the following standard features: 0.5K/1K words of EPROM, 25 bytes of RAM, 8-bit timer/counter, power-on reset, on-chip oscillator and clock circuitry. In addition, the GMS77C1000 and GMS77C1001 supports power saving modes to reduce power consumption.
Device name GMS77C1000 GMS77C1001 ROM Size 0.5K words(12-bit) 1K words(12-bit) RAM Size 25 bytes 25 bytes Package 18 PDIP, SOP or 20 SSOP 18 PDIP, SOP or 20 SSOP
1.2 Features
* High-Performance RISC CPU: 12-bit wide instructions and 8-bit wide data path 33 single word instructions 0.5K/1K words on-chip program memory 25 bytes on-chip data memory Minimum instruction execution time 200ns @20MHz Operating speed: DC - 20 MHz clock input Seven special function hardware registers Two-level hardware stack * CMOS Technology: * Peripheral Features: Twelve programmable I/O lines One 8-bit timer/counter with 8-bit programmable prescaler Power-On Reset (POR) Power Fail Detector : noise immunity circuit 2 level detect ( 3V, 2.5V ) Low-power, high-speed CMOS EPROM technology Fully static design Wide-operating range: 2.5V to 5.5V @ RC, XT, LF 4.5V to 5.5V @ HF Internal Reset Timer (IRT) Watchdog Timer (WDT) with on-chip RC oscillator Programmable code-protection Power saving SLEEP mode Selectable oscillator options: Configuration word
RC: Low-cost RC oscillator (200KHz~4MHz) XT: Standard crystal/resonator (455KHz~4MHz) HF: High-speed crystal/resonator (4~20MHz) LF: Power saving, low-frequency crystal/resonator (32~200KHz)
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GMS77C1000/GMS77C1001
2. BLOCK DIAGRAM
OPTION
STATUS ALU
8-bit Timer/ Counter
STACK 1 Data Memory STACK 2
PC
Power Fail Detector System controller Clock Generator Timing Control
W WDT/ TMR0 Prescaler Watch-dog Timer
Program Memory WDT time out
RESET Xin Xout
Instruction Decoder
VDD VSS Power Supply
Configuration Word
RA
TRISA
RB
TRISB
RA0 RA1 RA2 RA3
EC0
RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7
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3. PIN ASSIGNMENT
18 PDIP or SOP
RA2 RA3 EC0 RESET/VPP VSS RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RA1 RA0 Xin Xout VDD RB7 RB6 RB5 RB4
20 SSOP
RA2 RA3 EC0 RESET/VPP VSS VSS RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1 RA0 Xin Xout VDD VDD RB7 RB6 RB5 RB4
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GMS77C1000/GMS77C1001
4. PACKAGE DIAGRAM
18 PDIP
unit: inch MAX MIN
TYP 0.300 0.925 MIN 0.020 0.895 MAX 0.180 0.270 0.245
0.140
0.120
0.022 0.0 15 0.065 0.045 TYP 0.10 0 ~ 15
5 0.01 8 0.00
18 SOP
0.292
0.299
0.104 0.097
0.0115 0.005
0.461 0.451
0.410 0.400
0.0091
0.0125
0.029 0.014
0 ~ 8 TYP 0.050 0.040 0.024
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20 SSOP
unit: inch MAX MIN
0.212 0.205 0.311 0.301
0.078 0.068
0.008 0.002
0.289 0.278
0.008
TYP 0.0256
July. 2001 Ver. 1.1
0.004
0.015 0.010
0 ~ 8 0.037 0.025
5
GMS77C1000/GMS77C1001
5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. RA0~RA3: RA is an 4-bit, CMOS, bidirectional I/O port.
PIN NAME
VDD VSS RESET XIN XOUT RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 EC0
RA pins can be used as outputs or inputs according to "0" or "1" written the their Port Direction Register(TRISA). RB0~RB7: RB is a 8-bit, CMOS, bidirectional I/O port. RB pins can be used as outputs or inputs according to "0" or "1" written the their Port Direction Register(TRISB). EC0: EC0 is an external clock input to Timer0. It should be tied to VSS or VDD, if not in use, to reduce current consumption.
Function
Supply voltage Circuit ground Reset signal input/programming voltage input. This pin is an active low reset to the device. Voltage on the RESET pin must not exceed VDD to avoid unintended entering of programming mode. Oscillator crystal input/external clock source input Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, XOUT pin outputs CLKOUT which has 1/4 the frequency of XIN, and denotes the instruction cycle rate.
DIP, SOP Pin No.
14 5 4 16 15 17 18 1 2 6 7 8 9 10 11 12 13 3
SSOP Pin No.
15,16 5,6 4 18 17 19 20 1 2 7 8 9 10 11 12 13 14 3
In/Out
P P
Input Levels
-
I
ST
I
ST
O
-
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
TTL TTL
4-bit bi-directional I/O ports
TTL TTL TTL TTL TTL TTL
8-bit bi-directional I/O ports
TTL TTL TTL TTL ST
Clock input to Timer0. Must be tied to VDD or VSS, if not in use, to reduce current consumption.
TABLE 5-1 PINOUT DESCRIPTION
Legend : I =input, O = output, I/O = input/output, P = power, - = Not used, TTL = TTL input, ST = Schmitt Trigger input
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6. PORT STRUCTURES
* RESET
Internal RESET
VSS
* Xin, Xout
( XT, HF, LF Mode )
EN ( XT, HF, LF ) VDD
To Internal Clock
Xout
RF
VSS
Amplifier varies with the oscillation mode Xin
( RC Mode )
EN ( RC ) VDD
/4
Xout
VSS Internal Capacitance ( appx. 6pF )
To Internal Clock
Xin
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GMS77C1000/GMS77C1001
* RA0~3/RB0~7
Data Reg. Data Bus
VDD
Direction Reg. Data Bus
Data Bus Read
VSS
* EC0
VDD
Timer Counter Clock Input
EC0
VSS
8
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage .............................................. -0 to +7.5 V Storage Temperature ................................-65 to +125 C Voltage on RESET with respect to VSS .......0.3 to 13.5V Voltage on any pin with respect to VSS. -0.3 to VDD+0.3 Maximum current out of VSS pin ........................150 mA Maximum current into VDD pin ..........................100 mA Maximum output current sunk by (IOL per I/O Pin)25 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................20 mA Maximum current (IOL) .................................... 120 mA Maximum current (IOH)...................................... 80 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Symbol Condition Min. Supply Voltage VDD fXIN=20MHz fXIN=4MHz RC Mode Operating Frequency fXIN XT Mode HF Mode LF Mode Operating Temperature TOPR 4.5 2.5 0.2 0.455 4 32 -40 Max. 5.5 V 5.5 4 4 20 200 85 KHz C MHz Unit
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GMS77C1000/GMS77C1001
7.3 DC Characteristics (1)
* (TA=-40C~+85C)
Specification Parameter Supply Voltage XT, RC, LF HF VDD start voltage to ensure Power-On Reset VDD rise rate RAM Data Retention Voltage Power Fail Detection Normal Level Low Level Supply Current XT, RC4 HF LF Power Down Current
1. 2. 3. 4. 5.
Symbol
Test Condition
Min
Typ1
Max
Unit
VDD
2.5 4.5
5.5 5.5 VSS 1.5 -
V
VPOR SVDD2 VDR
0.05 -
V V/mS V
VPFD
-
3 2.5
-
V
IDD3
XIN = 4MHz, VDD = 5V XIN = 20MHz, VDD = 5V XIN = 32KHz, VDD = 3V, WDT Disabled
-
1.8 9.0 17 10 0.25
3.3 20 40 20 5
mA mA uA uA
IPD5
VDD = 3V, WDT Enabled VDD = 3V, WDT Disabled
Data in "Typ" column is at 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This parameter is characterized but not tested. The test conditions for all IDD measurements in NOP execution are: XIN = external square wave; all I/O pins tristated, pulled to V SS, EC0 = VDD, RESET = VDD; WDT disabled/enabled as specified. Does not include current through Rext. The current through the resistor can be estimated by the formula; IR = VDD/2Rext (mA) Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS as like measurement conditions of supply current.
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7.4 DC Electrical Characteristics (2)
* (TA=-40C~+85C)
Specification Parameter Input High Voltage I/O Ports (TTL) RESET, EC0, (ST) XIN (ST) XIN (ST) Input Low Voltage I/O Ports (TTL) RESET, EC0, (ST) XIN (ST) XIN (ST) Hysteresis of Schmitt Trigger Inputs Input Leakage Current XIN (ST) Other Pins Output High Voltage I/O Ports XOUT Output Low Voltage I/O Ports XOUT
1. 2.
Symbol
Test Condition
Min
Typ1
Max
Unit
0.25VDD +0.8 VIH RC only XT, HF, LF 0.85VDD 0.85VDD 0.7VDD 0.15VDD VIL RC only XT, HF, LF VHYS VIN = VDD or VSS IL XT, HF, LF -3.0 -1.0 0.5 0.2 3.0 1.0 uA 0.15VDD2 VSS 0.15VDD 0.15VDD 0.3VDD V V VDD V
VOH
IOH = -5.0mA, VDD = 4.5V IOH = -5.0mA, VDD = 4.5V, RC osc. IOL = 8.0mA, VDD = 4.5V IOL = 600uA, VDD = 4.5V, RC osc.
VDD - 0.9
VDD
V
VOL
VSS
0.8
V
Data in "Typ" column is at 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This parameter are characterized but not tested.
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GMS77C1000/GMS77C1001
7.5 AC Electrical Characteristics (1)
* (TA=-40C~+85C) Specification Min DC DC DC DC 0.1 4.0 5.0 250 50 5 250 250 50 5 85 20 2 Typ Max 4.0 20 200 4.0 4.0 20 200 4.0 10,000 250 200 25 25 50
Parameter
Symbol
Test Condition XT osc mode
Unit MHz MHz KHz MHz MHz MHz KHz nS nS uS MHz nS nS uS nS nS uS nS nS nS
External Clock Input Frequency
FXIN
HF osc mode LF osc mode RC osc mode
Oscillator Frequency 1
FXIN
XT osc mode HF osc mode LF osc mode XT osc mode
External Clock Input Period
TXIN
HF osc mode LF osc mode RC osc mode
Oscillator Period 1
TXIN
XT osc mode HF osc mode LF osc mode XT osc mode
Clock in XIN Pin 1 Low to High Time
TXINL TXINH
HF osc mode LF osc mode XT osc mode
Clock in XIN Pin 1 Rise or Fall Time
1.
TXINR TXINF
HF osc mode LF osc mode
This parameter is characterized but not tested.
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7.6 AC Electrical Characteristics (2)
* (TA=-40C~+85C)
Specification Symbol TRESET TWDT TIRT TEC0H TEC0L Test Condition VDD = 5V VDD = 5V VDD = 5V TCY = 4 X TXIN Min 100 10 5 Typ2 14 7 Max 20 10 Unit nS mS mS
Parameter 1 RESET Pulse Width (Low) Watchdog Timer Time-Out Period ( No-prescaler ) Internal Reset Timer Period EC0 High or Low Pulse Width No Prescaler With Prescaler EC0 Period No Prescaler With Prescaler
1. 2.
10 0.5TCY + 20
-
-
nS
TEC0P
N = Prescaler Value ( 1,2,4,......256 )
20 (TCY+40) / N
-
-
nS
These parameters are characterized but not tested. Data in "Typ" column is at 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TXIN
TXINH
TXINL 0.85VDD 0.15V
XIN
TXINR
TXINF
TRESET
RESET
0.15VDD
TEC0H
TEC0H 0.85VDD
EC0
TEC0P
0.15VDD
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GMS77C1000/GMS77C1001
7.7 Typical Characteristics
These graphs and tables are for design guidance only and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
Operating Area
fXIN (MHz) 24 20 16 12 8 4 0 2 3 4 5 6 VDD (V) Ta= 25C IDD (mA) 4
Normal Operation IDD-VDD
Ta=25C
fXIN = 20MHz 3 2 1 0 2 3 4 5 4MHz 32KHz VDD 6 (V)
IOL-VOL, VDD=5V
IOL (mA) Ta=25C 40 18 32 24 16 6 8 0 0.4 0.8 1.2 1.6 VOL 2.0 (V) 0 12 IOL (mA)
IOL-VOL, VDD=3V
Ta=25C
0.4
0.8
1.2
1.6
VOL 2.0 (V)
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IOH-VOH, VDD=5V
IOH (mA) -20 -16 -6 -12 -4 -8 -4 0 0.5 1.0 1.5 VDD-VOH (V) -2 Ta=25C IOH (mA) -8
IOH-VOH, VDD=3V
Ta=25C
0 0.5 1.0 1.5
2.0
VDD-VOH (V)
FOSC (MHz) 7.5 6.0 4.5 3.0 1.5
Typical RC Oscillator Frequency VS. VDD
Cext=0pF Ta=25C R=3.3K
FOSC (MHz) 4.5 4.0 3.5
Typical RC Oscillator Frequency VS. VDD
Cext=20pF Ta=25C R=3.3K
R=5K
3.0 2.5 2.0
R=5K
R=10K
R=10K
1.5 1.0
R=100K 0 2.5 3 3.5 4 4.5 5 5.5 VDD 6 (V)
0.5 0 2.5 3 3.5 4 4.5
R=100K 5 5.5 VDD 6 (V)
FOSC (MHz) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0
Typical RC Oscillator Frequency VS. VDD
Cext=100pF Ta=25C R=3.3K
FOSC (MHz) 0.8 0.7
Typical RC Oscillator Frequency VS. VDD
Cext=300pF Ta=25C R=3.3K
R=5K
0.6 0.5 0.4
R=5K
R=10K
0.3 0.2
R=10K
R=100K 2.5 3 3.5 4 4.5 5 5.5 VDD 6 (V)
0.1 0 2.5 3 3.5 4 4.5
R=100K 5 5.5 VDD 6 (V)
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GMS77C1000/GMS77C1001
Cext
Rext 3.3K
Average Fosc @ 5V,25C 7.48MHz 6.36MHz 4.04MHz 529KHz 4.60MHz 3.62MHz 2.14MHz 249KHz 1.75MHz 1.31MHz 734KHz 80KHz 702KHz 510KHz 283KHz 30KHz
0pF
5K 10K 100K 3.3K
20pF
5K 10K 100K 3.3K
100pF
5K 10K 100K 3.3K
300pF
5K 10K 100K
Table 7-1 RC Oscillator Frequencies
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8. ARCHITECTURE
8.1 CPU Architecture
The GMS700 core is a RISC-based CPU and uses a modified Harvard architecture. This architecture uses two separate memories with separate address buses, one for the program memory and the other for the data memory. This architecture adapts 33 single word instructions that are 12bit wide instruction and has an internal 2-stage pipeline (fetch and execute), which results in execution of one instruction per single cycle(200ns @ 20MHz) except for program branches. The GMS77C100X can address 1K x 12 Bits program memory and 25 Bytes data memory. And it can directly or indirectly address data memory. The GMS700 core has three special function registers PC, STATUS and FSR - in data memory map and has ATU (Address Translation Unit) to provide address for data memory and has an 8-bit general purpose ALU and working register(W) as an accumulator. The W register consists of 8-bit register and it can not be an addressed register.
Program Memory Address Instruction PC with 2-level Stack STATUS Immediate Data FSR Indirect Address
Instruction Decode & Control Unit
Control Signals
Address Translation Unit
ALU Status
W
ALU
Data Bus
Data Memory Bus
FIGURE 8-1 GMS700 CPU BLOCK DIAGRAM
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GMS77C1000/GMS77C1001
9. MEMORY
The GMS77C1000/1001 has separate memory maps for program memory and data memory. Program memory can only be read, not written to. It can be up to 1K words of program memory. Data memory can be read and written to 32 bytes including special function registers.
PC<9:0>
Stack Level 1
9.1 Program Memory
The program memory is organized as 0.5K, 12-bit wide words(GMS77C1000) and 1K, 12-bit wide words(GMS77C1001). The program memory words are addressed sequentially by a program counter. Incrementing at location 1FFH(GMS77C1000) or 3FFH (GMS77C1001) will cause a wrap around to 000H. Figure 9-1 and Figure 9-2 show a map of program memory. After reset, CPU begins execution from reset vector which is stored in address(1FFH: GMS77C1000, 3FFH: GMS77C1001).
000H
Stack Level 2
0FFH 100H
1FFH 200H 2FFH 300H On-chip Program Memory (Page 1) Reset Vector
PC<8:0>
3FFH
Stack Level 1 Stack Level 2 000H User Memory Space
FIGURE 9-2 GMS77C1001 PROGRAM MEMORY MAP AND STACK
9.2 Data Memory
On-chip Program Memory
0FFH 100H
The data memory consists of 25 bytes of RAM and seven special function registers. The data memory locations are addressed directly or indirectly by using FSR. Figure 9-3 shows a map of data memory. The special function registers are mapped into the data memory..
File Address 00H INDF TMR0 PCL STATUS FSR RA RB 0FH 10H 06H 07H 00H Special F u n c tio n Registers DATA MEMORY (SRAM) DATA MEMORY (SRAM)
1FFH
Reset Vector
FIGURE 9-1 GMS77C1000 PROGRAM MEMORY MAP AND STACK
01H 02H 03H 04H 05H 06H
1FH
FIGURE 9-3 GMS77C1000/1 DATA MEMORY MAP
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User Memory Space
On-chip Program Memory (Page 0)
GMS77C1000/GMS77C1001
9.3 Special Function Registers
This devices has seven special function register that are the INDF register, the Program Counter(PC), the STATUS register, File Select Register(FSR), 8-bit Timer(TMR0), and I/O data register(RA, RB). The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
Name TRIS OPTION INDF TMR0 PCL STATUS FSR RA RB Address N/A N/A 00H 01H 02H 03H 04H 05H 06H Bit7 Bit6 Bit5 Bit4
the device (Table 9-1). TMR0, RA and RB are not in the G700 CPU. They are located in each peripheral function blocks. All special function register are placed on data memory map. The INDF register is not a physical register and this register is used for indirect addressing mode...
Bit3 Bit2 Bit1 Bit0 Power-On Reset 1111 1111 0011 1111 xxxx xxxx xxxx xxxx 1111 1111 RESET and WDT Reset 1111 1111 0011 1111 uuuu uuuu uuuu uuuu 1111 1111 000q quuu 1uuu uuuu ---- uuuu uuuu uuuu
I/O control registers (TRISA, TRISB) Contains control bits to configure Timer0, Timer0/WDT prescaler and PFD Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8bits of PC PA0 TO PD Z DC C
0001 1xxx 1xxx xxxx
Indirect data memory address pointer RB7 RB6 RB5 RB4 RA3 RB3 RA2 RB2 RA1 RB1 RA0 RB0
---- xxxx xxxx xxxx
TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY
Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as `0' x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.
9.3.1 INDF Register The INDF register is not physically implemented register, used for indirect addressing mode. If the INDF register are accessed, CPU goes to indirect addressing mode. Then CPU accesses the Data memory which address is the contents of FSR. If the INDF register are accessed in indirect addressing mode(I.e., FSR=00H), 00H will be loaded into data bus. This time, note the arithmetic status bits of STATUS register may be affected. The FSR<4:0> bits are used to select data memory addresses 00H to 1FH. GMS77C1000 and GMS77C1001 do not use banking. FSR<7:5> are unimplemented and read as '1's.
1FH Direct Addressing 4 (opcode) 0 Indirect Addressing (FSR) 0
4
location select
00H
location select
Data Memory
0FH 10H
FIGURE 9-4 DIRECT/INDIRECT ADDRESSING
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9.3.2 TMR0 Register The TMR0 register is a data register for 8-bit timer/ counter. In reset state, the TMR0 register is initialized with "00H". 9.3.3 Program Counter (PC)
jump instruction
9 PC 8 PCL 0
Instruction Word
PA0
The program counter contains the 10-bit address of the instruction to be executed(9-bit address for GMS77C1000).
subroutine call Instruction
The lower 8 bits of the program counter are contained in the PCL register which can be provided by the instruction word for a call instruction, or any instruction where the PCL is the destination while the ninth bit of the program counter comes from the page address bit - PA0 of the STATUS register(GMS77C1001 only). This is necessary to cause program branches across program memory page boundaries. Prior to the execution of a branch operation, the user must initialize the PA0 bit of STATUS register. The eighth bit of the program counter can come from the instruction word by execution of goto instruction, or can be cleared by execution of call or any instruction where the PCL is the destination. In reset state, the program counter is initialized with "1FFH"(GMS77C1000) or "3FFH"(GMS77C1001).
Note: Because PC<8> is cleared in the subroutine call instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long).
jump instrunciton
8 PC PCL 0
9 PC
8
7 PCL
0
Instruction Word Reset to `0'
PA0
FIGURE 9-6 LOADING OF BRANCH INSTRUCTION GMS77C1001
9.3.4 Stack Operation The GMS77C1000/1001 have a 2-level hardware stack. The stack register consists of two 9-bit save registers(GMS77C1000), 10-bit save registers(GMS77C1001). A physical transfer of register contents from the program counter to the stack or vice versa, and within the stack, occurs on call and return instructions. If more than two sequential call instructions are executed, only the most recent two return address are stored. If more than two sequential return instructions are executed, the stack will be filled with the address previously stored in level 2. The stack cannot be read or written by program.
GMS77C1001(GMS77C1000) 9(8) 0 PC subroutine call STACK LEVEL1 return
Instruction Word
subroutine call instruction
8 PC 7 PCL 0
subroutine call STACK LEVEL2
return
Instruction Word Reset to `0'
FIGURE 9-7 OPERATION OF 2-LEVEL STACK FIGURE 9-5 LOADING OF BRANCH INSTRUCTION GMS77C1000
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9.3.5 STATUS Register This register contains the arithmetic status of the ALU, the RESET status, and the page select bit for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. There-
fore, the result of an instruction with the STATUS register as destination may be different than intended. It is recommended that only instructions that do not affect status of CPU be used on STATUS register. Care should be exercised when writing to the STATUS register as the ALU status bits are updated upon completion of the write operation, possibly leaving the STATUS register with a result that is different than intended. In reset state, the STATUS register is initialized with "00011XXXB".
R/W bit7 PA0
R TO
R PD
R/W Z
R/W DC
R/W C bit0
ADDRESS ; 03H RESET VALUE : 0001_1XXX R = Readable bit W = Writable bit
PA0: Program memory page select bits 0 = page 0 (000h - 1FFh) - GMS77C1000/1001 1 = page 1 (200h - 3FFh) - GMS77C1001 TO: Time-overflow bit 1 = After power-up, watchdog clear instruction, or entering power-down mode 0 = A watchdog timer time-overflow occurred PD: Power-down bit 1 = After power-up or by the watchdog clear instruction 0 = By execution of power-down mode Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for addition and subtraction) addition 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur subtraction 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for additon,subtraction and rotation) addition 1 = A carry occurred 0 = A carry did not occur subtraction 1 = A borrow did not occur 0 = A borrow occurred rotation Load bit with LSB or MSB, respectively
FIGURE 9-8 STATUS REGISTER
9.3.6 FSR Register The FSR register is an 8-bit register. The lower 5 bits are used to store indirect address for data memory. The upper 3 bits are unimplemented and read as "0". Figure 9-9
shows how the FSR register can be used in indirect addressing mode. In reset state, the FSR register is initialized with "1XXX_XXXXB".
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11
Instruction Word 54 OPCODE
0
8 -
4 FSR
0 Address : 04H RESET Value: 1XXX_XXXXB
Direct Addressing mode 0 1
Indirect Addressing mode
Data Memory Address
FIGURE 9-9 FSR REGISTER AND DIRECT/INDIRECT ADDRESSING MODE
9.3.7 OPTION Register The OPTION register consists of 8-bit write-only register and can not addressed. This register is able to control the status of PFD, TMR0/WDT prescaler and TMR0.
To modify the OPTION register, the content of W register are transferred to the OPTION register by executing the OPTION instruction. In reset state, the OPTION register is initialized with "00111111B" .
W
W
W T0CS 5
W T0SE 4
W PSA 3
W PS2 2
W PS1 1 PS2-PS0: Bit Value 000 001 010 011 100 101 110 111
W PS0 bit0
ADDRESS ; 03H RESET VALUE : 0011_1111 W = Writable bit -n = Value at POR reset
LOWOPT PFDEN bit7 LOWOPT: 6
Power-fail detection level select bit. 1 = Lowered detection level (2.5V @ 5V) 0 = Normal detection level (3V @ 5V) Power-fail detection enable bit 1 = Enable power-fail detection 0 = Disable power-fail detection Timer 0 clock source select bit 1 = Transition on EC0 pin 0 = Internal instruction cycle clock Timer 0 source edge select bit 1 = Increment on high-to-low transition on EC0 0 = Increment on low-to-high transition on EC0 Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to the Timer 0
Prescaler rate select bits) Timer 0 rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT rate 1:2 (Typ. 28mS) 1:4 (Typ. 56mS) 1:8 (Typ. 112mS) 1:16 (Typ. 224mS) 1:32 (Typ. 448mS) 1:64 (Typ. 896mS) 1:128 (Typ. 1792mS) 1:256 (Typ. 3584mS)
PFDEN:
T0CS:
T0SE:
PSA:
FIGURE 9-10 OPTION REGISTER
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10. I/O PORTS
The GMS77C1000/1001 has a 4-bit I/O port(RA) and a 8bit I/O port(RB). All pin have data(RA,RB) and direction(TRISA,TRISB) registers which can assign these ports as output or input. A "0" in the port direction registers configure the corresponding port pin as output. Conversely, write "1" to the corresponding bit to specify it as input pin (Hi-Z state). For example, to use the even numbered bit of RB as output ports and the odd numbered bits as input ports, write "55H" to TRISB register during initial setting as shown in Figure 10-1. All the port direction registers in the GMS77C1000/1001 have "1" written to them by reset function. This causes all port as input.
Write "55H" to port RB direction register
7 6 1 5 0 4 1 3 0 2 1 1 0 0 1
10.2 Port RB
RB is an 8-bit I/O register. Each I/O pin can independently used as an input or an output through the port direction register, TRISB. A "0" in the TRISB register configure the corresponding port pin as output. Conversely, write "1"to the corresponding bit to specify it as input pin.
ADDRESS : 06H RESET VALUE : Undefined
4 3 2 1 0
RB Data Register
7 6 5
RB R B 7 R B 6 R B 5 R B 4 R B 3 R B 2 R B 1 R B 0 RB Direction Register TRISB ADDRESS : N/A RESET VALUE : FFH
FIGURE 10-3 RB PORT REGISTERS
TRISB
0
PORT RB O U T IN O U T IN O U T IN O U T IN
Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT
10.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 10-4. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction. The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output..
10.1 Port RA
RA is a 4-bit I/O register. Each I/O pin can independently used as an input or an output through the port direction register, TRISA. A "0" in the TRISA register configure the corresponding port pin as output. Conversely, write "1"to the corresponding bit to specify it as input pin. Bits 7-4 are unimplemented and read as '0's.
RA Data Register
3 2 1 0
ADDRESS : 05H RESET VALUE : Undefined
RA R A 3 R A 2 R A 1 R A 0 RA Direction Register TRISA ADDRESS : N/A RESET VALUE : 0FH
10.4 I/O Successive Operations
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 10-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed.
FIGURE 10-2 RA PORT REGISTERS
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GMS77C1000/GMS77C1001
Data Reg. Data Bus
VDD
Direction Reg. Data Bus
Data Bus Read
VSS
FIGURE 10-4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN Power-On Reset 1111 1111 RA2 RB2 RA1 RB1 RA0 RB0 ---- xxxx xxxx xxxx RESET and WDT Reset 1111 1111 ---- uuuu uuuu uuuu
Name TRIS RA RB
Address N/A 05H 06H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I/O control registers (TRISA, TRISB) RB7 RB6 RB5 RB4 RA3 RB3
TABLE 10-1 SUMMARY OF PORT REGISTERS
Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as `0', x = unknown, u = unchanged.
Otherwise, the previous state of that pin may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction fetched
PC
output RB
PC+1
read RB port
PC+2
no operation
PC+3
no operation
This example shows a write to RB followed by a read from RB.
RB7:RB0 Port pin written here Port pin read here
FIGURE 10-5 SUCCESSIVE I/O OPERATION
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11. TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
* 8-bit timer/counter register, TMR0 * 8-bit software programmable prescaler * Internal or external clock select
* Edge select for external clock Figure 11-1 is a simplified block diagram of the Timer0 module, while Figure 11-2 shows the electrical structure of the Timer0 input.
TCY ( = FOSC/4) Data bus
0 1 1 EC0 pin T0SE
8 MUX Sync with Internal Clocks (2cycle delay) TMR0 reg
MUX
0
T0CS PSA
0 1
MUX
8-bit Prescaler 8 8 - to - 1 MUX
clear
Watchdog Timer
PS2:PS0
WDT Enable bit
PSA
0 1
MUX
PSA
WDT Time-Out
FIGURE 11-1 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
P
RIN
Noise Filter
(1)
ECO pin
N
Schmitt Trigger Input Buffer
Note 1: ESD protection circuits
FIGURE 11-2 ELECTRICAL STRUCTURE OF EC0 PIN
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11.1 Timer Mode
If the OPTION register bit5(T0CS) is cleared, the timer mode is selected and is operated with internal system clock (TCY). The Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles. The user can work around this by writing an adjusted value to the TMR0 register. Figure 11-3 and Figure 11-4 show the timing diagram of Timer. - No Prescaler (PSA=0) Timer will increment every instruction cycle(Q4).
- With Prescaler (PSA=1) Timer will increment with prescaler division ratio. @ PS2~PS0 = (1:2) ~ (1:256)Counter Mode
11.2 Counter Mode
If the OPTION register bit5(T0CS) is set, the counter mode is selected and operates with event clock input. In this mode, Timer0 will increment either on every rising or falling edge of pin EC0. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC (Program Counter) Instruction Fetch Instruction Executed TMR0
T0
PC-1
PC
[ W ' TMR0 ]
PC+1
[ TMR0 ' W ]
PC+2
[ TMR0 ' W ]
PC+3
[ TMR0 ' W ]
PC+4
[ TMR0 ' W ]
PC+5
[ TMR0 ' W ]
PC+6
Write TMR0 Read TMR0 executed reads NT0
T0+1 T0+2
Read TMR0 reads NT0
NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0+1 reads NT0+2
NT0+1 NT0+2
Timer0 Clock
increment inhibited
FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC (Program Counter) Instruction Fetch Instruction Executed
PC-1
PC
[ W ' TMR0 ]
PC+1
[ TMR0 ' W ]
PC+2
[ TMR0 ' W ]
PC+3
[ TMR0 ' W ]
PC+4
[ TMR0 ' W ]
PC+5
[ TMR0 ' W ]
PC+6
Write TMR0 Read TMR0 executed reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0+1 reads NT0+2
TMR0
T0
T0+1
NT0
NT0+1
Timer0 Clock
increment inhabited
FIGURE 11-4 TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
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Name TMR0
Address 01H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On Reset xxxx xxxx
RESET and WDT Reset uuuu uuuu 0011 1111
8-bit real-time clock/counter LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0
OPTION N/A
0011 1111
TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0
Legend: x = unknown, u = unchanged.
11.3 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 11.3.1 External Clock Synchronization The synchronization of EC0 input with the internal phase clocks is accomplished by sampling EC0 clock or the prescaler output on the Q2 and Q4 falling of the internal phase clocks. After the synchronization, counter increments on the next instruction cycle (Q4). There is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incrementing. Figure 11-5 shows the syn-
chronization and the increment of the counter mode. * EC0 clock specification - No Prescaler (PSA = 0) High or low time(min) 2TXIN + 20ns - With Prescaler (PSA = 1) High or low time(min) 4TXIN + 40ns But, there is a noise filter on the EC0 pin, the minimum low or high time(10ns) should be required. 11.3.2 Timer0 Increment Delay Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incrementing. Figure 11-5 shows the delay from the external clock edge to the timer incrementing.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Prescaler Output(2)
(1)
Small Pulse misses sampling
External Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0
(3)
T0
T0+1
T0+2
Note 1: Delay from clock input change to TMR0 increment is 3TXIN to 7TXIN . (Duration of Q = TXIN). Therefore, the error in measuring the interval between two edges on TMR0 input = 4TXIN max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
FIGURE 11-5 TIMER0 TIMING WITH EXTERNAL CLOCK
11.4 Prescaler
The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is neither readable nor writable. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When the prescaler is assigned to the Timer0 module, prescale values of 1:2,
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1:4,..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When as-
signed to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. On a RESET, the prescaler contains all '0's.
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12. CONFIGURATION AREA
The device configuration area can be programmed or left unprogrammed to select device configurations such as oscillator type, security bit or watchdog timer enable bit.
bit11
AAAH AAAH+1 AAAH+2 AAAH+3
-
43 ID0 ID1 ID2 ID3
bit0
Four memory locations [AAAH ~ (AAA+3)H] are designated as customer ID recording locations where the user can store check-sum or other customer identification numbers. These area are not accessible during normal execution but are readable and writable during program/verify mode. It is recommended that only the 4 least significant bits of ID recording locations are used.
FFFH
Configuration Word
FIGURE 12-1 DEVICE CONFIGURATION AREA
bit11 Configuration Word
-
4
3
CP
2
1
bit0 Address : FFFH
WDTE FOSC1 FOSC0
Unimplemented, read as `0' bit 3 CP : Code protection bit. 1 = Code protection disabled 0 = Code protection enabled WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator selection bits 11 = RC oscillator 10 = HF oscillator 01 = XT oscillator 00 = LF oscillator
bit 2
bit 1-0
FIGURE 12-2 CONFIGURATION WORD FOR GMS77C1000/1001
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13. OSCILLATOR CIRCUITS
GMS77C100X supports four user-selectable oscillator modes. The oscillator modes are selected by programming the appropriate values into the configuration word. XT : Crystal/Resonator HF : High Speed Crystal/Resonator LF : Low Speed and Low Power Crystal RC : External Resistor/Capacitor
Osc Type XT Resonator Freq 455 kHz 2.0 MHz 4.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Cap.Range C1 22-100 pF 15-68 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF Cap. Range C2 22-100 pF 15-68 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF
HF
13.1 XT, HF or LF Mode
In XT, LF or HF modes, a crystal or ceramic resonator is connected to the XIN and XOUT pins to establish oscillation (Figure 13-1). The GMS77C100X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. Bits 0 and 1 of the configuration register (FOSC1:FOSC2) are used to configure the different external resonator/crystal oscillator modes. These bits allow the selection of the appropriate gain setting for the internal driver to match the desired operating frequency. When in XT, LF or HF modes, the device can have an external clock source drive the XIN pin (Figure 13-2). In this case, the XOUT pin should be left open.
C1(1)
TABLE 13-1 CAPACITOR SELECTION FOR CERAMIC RESONATORS
Note: These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
Osc Type LF
Crystal Freq 32 kHz1 100 kHz 200 kHZ 100 kHz 200 kHz 455 kHz 1 MHz 2 MHz 4 MHz 4 MHz 8 MHz 20 MHz
Cap.Range C1 15 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-47 pF 15-30 pF 15-30 pF 15-30 pF
Cap. Range C2 15 pF 30-47 pF 15-82 pF 200-300 pF 100-200 pF 15-100 pF 15-30 pF 15-30 pF 15-47 pF 15-30 pF 15-30 pF 15-30 pF
XT
XOUT SLEEP XTAL XIN RF(2) To internal logic
C2(1)
HF
Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: RF varies with the crystal chosen (approx. value = 9 M).
TABLE 13-2 CAPACITOR SELECTION FOR CRYSTAL
1. For VDD > 4.5V, C1 = C2 30 pF is recommended.
FIGURE 13-1 CRYSTAL OR CERAMIC RESONATOR (HF, XT OR LF OSC CONFIGURATION)
Clock from ext. system OPEN
XIN
Note: These values are for design guidance only. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. If you change from this device to another device, please verify oscillator characteristics in your application.
GMS77C100X
XOUT
13.2 RC Oscillation Mode
The external RC oscillator mode provides a cost-effective approach for applications that do not require a precise operating frequency. In this mode, the RC oscillator frequen-
FIGURE 13-2 EXTERNAL CLOCK INPUT OPERATION (HF, XT OR LF OSC CONFIGURATION)
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cy is a function of the supply voltage, the resistor(R) and capacitor(C) values, and the operating temperature. In addition, the oscillator frequency will vary from unit to unit due to normal manufacturing process variations. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low C values. The external R and C component tolerances contribute to oscillator frequency variation as well. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 13-3 shows how the R is connected to the GMS77C100X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Table 13-3 shows recommended value of Rext and Cext. Although the oscillator will operate with no external capacitor (Cext = 0 pF), it is recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.
Cext Rext 3.3K 5K 10K 100K 3.3K 5K 10K 100K 3.3K 5K 10K 100K 3.3K 5K 10K 100K Average FXIN @ 5V, 25C 7.48MHz 6.36MHz 4.04MHz 529KHz 4.60MHz 3.62MHz 2.14MHz 249KHz 1.75MHz 1.31MHz 734KHz 80KHz 702KHz 510KHz 283KHz 30KHz
The Electrical Specifications sections show R frequency variation from part to part due to normal process variation.
Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on the XOUT pin, and can be used for test purposes or to synchronize other logic.
VDD
Rext XIN
N Internal Clock
Cext
FXIN/4
XOUT
FIGURE 13-3 RC OSCILLATION MODE
0pF
20pF
100pF
300pF
TABLE 13-3 RC OSCILLATION FREQUENCIES
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14. RESET
GMS77C100X devices may be reset in one of the following ways:
- Power-On Reset (POR) - Power-Fail detect reset (PFDR) - RESET (normal operation) - RESET wake-up reset (from SLEEP) - WDT reset (normal operation) - WDT wake-up reset (from SLEEP)
Table 14-2 lists a full description of reset states of all registers. Figure 14-1 shows a simplified block diagram of the on-chip reset circuit.
Condition Power-On Reset RESET reset or PFD reset (normal operation) RESET wake-up or PFD reset (from SLEEP) WDT reset (normal operation) WDT wake-up (from SLEEP) PCL Addr: 02H 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 STATUS Addr: 03H 0001 1xxx 000u uuuu1 0001 0uuu 0000 uuuu2 0000 0uuu
Each one of these reset conditions causes the program counter to branch to reset vector address. (GMS77C1000 is 1FFH and GMS77C1001 is 3FFH ). Table 14-1 shows these reset conditions for the PCL and STATUS registers. Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-On Reset (POR), PFDR, RESET or WDT reset. A RESET or WDT wake-up from SLEEP also results in a device reset, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different reset conditions. These bits may be used to determine the nature of the reset.
Register W TRIS OPTION INDF TMR0 PCL1 STATUS1 FSR PORTA PORTB General Purpose Register Files Address N/A N/A N/A 00H 01H 02H 03H 04H 05H 06H 07-1FH
TABLE 14-1 RESET CONDITIONS FOR SPECIAL REGISTERS
1. TO and PD bits retain their last value until one of the other reset conditions occur. 2. The CLRWDT instruction will set the TO and PD bits. Legend : x = unknown, u = unchanged.
Power-On Reset xxxx xxxx 1111 1111 0011 1111 xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 1xxx xxxx ---- xxxx xxxx xxxx xxxx xxxx
Wake-up Reset uuuu uuuu 1111 1111 0011 1111 uuuu uuuu uuuu uuuu 1111 1111 100q quuu 1uuu uuuu ---- uuuu uuuu uuuu uuuu uuuu
RESET, PFDR, WDT Reset uuuu uuuu 1111 1111 0011 1111 uuuu uuuu uuuu uuuu 1111 1111 000q quuu 1uuu uuuu ---- uuuu uuuu uuuu uuuu uuuu
TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS
1. See Table 14-1 for reset value for specific conditions. Legend : - = unimplemented, read as `0', x = unknown, u = unchanged. q = see the tables in Section 17 for possible values.
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Power-On RESET
VDD
WDT Time-Overflow
Power-Fail Detect Noise Filter
RESET/VPP pin
S R
Q Q
Internal RESET
WDT On-Chip RC OSC
reset
clear Internal RESET Timer ( 8-bit asyn. ripple counter )
FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
14.1 Power-On Reset (POR)
The GMS77C100X family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the RESET/VPP pin to VDD. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 14-1.
The Power-On Reset circuit and the Internal Reset Timer circuit are closely related. On power-up, the reset latch is set and the IRT is reset. The IRT timer begins counting once it detects RESET to be high. After the time-out period, which is typically 7 ms (oscillation stabilization time), it will reset the reset latch and thus end the on-chip reset signal.
VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET
FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO VDD)
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GMS77C1000/GMS77C1001
VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET
FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): FAST VDD RISE TIME
VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET
- When VDD rise slowly, the TIRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, V1 VDDmin.
FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): SLOW VDD RISE TIME
A power-up example where RESET is not tied to VDD is shown in Figure 14-2. VDD is allowed to rise and stabilize before bringing RESET high. The chip will actually come out of reset TIRT after RESET goes high and POR, PFDR is released. In Figure 14-3, the on-chip Power-On Reset feature is being used (RESET and VDD are tied together). The VDD is stable before the internal reset timer times out and there is no problem in getting a proper reset. However, Figure 144 depicts a problem situation where VDD rises too slowly. The time between when the IRT senses a high on the RESET/VPP pin, and when the RESET/VPP pin (and VDD) actually reach their full value, is too long. In this situation,
when the internal reset timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external R circuits be used to achieve longer POR delay times (Figure 14-5).
Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.
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The POR circuit does not produce an internal reset when VDD declines.
VDD VDD
14.2 Internal Reset Timer (IRT)
The Internal Reset Timer (IRT) provides a fixed 7 ms nominal time-out on reset. The IRT operates on an internal RC oscillator. The processor is kept in RESET as long as the IRT is active. The IRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip IRT keeps the device in a RESET condition for approximately 7 ms after the voltage on the RESET/VPP pin has reached a logic high (VIH) level and POR released. Thus, external RC networks connected to the RESET input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. The IRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the GMS77C100X from SLEEP mode automatically.
D
R R1 RESET
C
- External Power-On Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. - R < 40 k is recommended to make sure that voltage drop across R does not violate the device electrical specification. - R1 = 100W to 1 kW will limit any current flowing into RESET from external capacitor C in the event of RESET pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
FIGURE 14-5 EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER- UP)
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GMS77C1000/GMS77C1001
15. WATCHDOG TIMER (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the XIN pin. That means that the WDT will run even if the clock on the XIN and XOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Figure 12-2). Refer to the GMS77C100X Programming Specifications to determine how to access the configuration word. caler with a division ratio of up to 1:256 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 3.5 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.
15.2 WDT Programming Considerations
The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.
15.1 WDT Period
The WDT has a nominal time-out period of 14 ms, (with no prescaler). If a longer time-out period is desired, a pres-
SLEEP From TMR0 Clock Source Watchdog Timer 8-bit asynchronous ripple counter clear enable 8 - to - 1 MUX PSA
0 1 0 1
PSA clearing WDT MUX Postscaler 8 PS2:PS0 To TMR0 PSA
on-chip RC-OSC
MUX WDTE WDT Time-Out
SLEEP
clearing WDT
FIGURE 15-1 WATCHDOG TIMER BLOCK DIAGRAM Power-On Reset 0011 1111 RESET and WDT Reset 0011 1111
Name OPTION
Address N/A
Bit7 LOWOPT
Bit6
Bit5
Bit4 T0SE
Bit3 PSA
Bit2 PS2
Bit1 PS1
Bit0 PS0
PFDEN T0CS
TABLE 15-1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
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16. Power-Down Mode (SLEEP)
For applications where power consumption is a critical factor, device provides power down mode with Watchdog operation. Executing of SLEEP Instruction is entrance to SLEEP mode. In the SLEEP mode, oscillator is turn off and system clock is disable and all functions is stop, but all registers and RAM data is held. The wake-up sources from SLEEP mode are external RESET pin reset and watchdog time-overflow reset. but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT timeout does not drive the RESET pin low. For lowest current consumption while powered down, the EC0 input should be at VDD or VSS and the RESET pin must be at a logic high level .
16.1 SLEEP
The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared
~ ~
Oscillator (XIN pin) Internal System Clock Instruction
Fetch SLEEP
~ ~
Execute SLEEP
~ ~ ~ ~
Fetch RESET vector
~~~ ~~~
~ ~
~ ~
RESET Internal RESET
TIRT
FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET
~ ~
~ ~ ~ ~
Oscillator (XIN pin) Internal System Clock Instruction
Fetch SLEEP
~ ~
Execute SLEEP
~ ~ ~ ~
Fetch RESET vector
~~~ ~~~
WDT Overflow Internal RESET
FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET
~~ ~~
~~ ~~
TIRT
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16.2 Wake-up From SLEEP
The device can wake up from SLEEP through one of the following events: 1. An external reset input on RESET pin. 2. A Watchdog Timer time-out reset (if WDT was enabled). 3. PFD reset Both of these events cause a device reset. The TO and PD bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.
from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow.
Note: In the SLEEP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the SLEEP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
16.3 Minimizing Current Consumption
The SLEEP mode is designed to reduce power consumption. To minimize current drawn during SLEEP mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing
If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low.
VDD INPUT PIN internal pull-up OPEN INPUT PIN VDD VDD i=0
VDD
O
O
i GND VDD
i
Very weak current flows
X
Weak pull-up current flows
X
OPEN
i=0
GND
O
O
When port is configure as an input, input level should be closed to 0V or 5V to avoid power consumption.
FIGURE 16-3 APPLICATION EXAMPLE OF UNUSED INPUT PORT
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OUTPUT PIN ON OPEN ON OFF i GND VDD ON OFF OFF
OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD
O
OFF
X
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port.
In the left case, much current flows from port to GND.
FIGURE 16-4 APPLICATION EXAMPLE OF UNUSED OUTPUT PORT
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17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)
The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a RESET or Watchdog Timer (WDT) reset, or a RESET or WDT wake-up reset.
TO 1 u 1 0 0 PD 1 u 0 1 0 RESET was caused by Power-up(POR) RESET or PFD reset (normal operation)1 RESET Wake-up or PFD reset (from SLEEP) WDT reset (normal operation) WDT wake-up reset (from SLEEP)
Table 17-2.
Event Power-up WDT Time-out SLEEP instruction CLRWDT instruction TO 1 0 1 1 PD 1 u 0 1 No effect on PD Remarks
TABLE 17-2 EVENTS AFFECTING TO/PD STATUS BITS
TABLE 17-1 TO/PD STATUS AFTER RESET
1. The TO and PD bits maintain their status (u) until a reset occurs. A low-pulse on the RESET input does not change the TO and PD status bits.
Note: A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit.
These STATUS bits are only affected by events listed in
Table 14-1 lists the reset conditions for the special function registers, while Table 14-2 lists the reset conditions for all the registers.
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18. POWER FAIL DETECTION PROCESSOR
GMS77C1000X has an on-chip power fail detection circuitry to immunize against power noise. If VDD falls below a level for longer 100ns, the power fail detection processor may reset MCU and preserve the device from the malfunction due to Power Noise.
OPTION Register
LOWOPT PFDEN bit7 bit 7 6
T0CS 5
T0SE 4
PSA 3
PS2 2
PS1 1
PS0 bit0
LOWOPT: Power-fail detection level select bit. 1 = Lowered detection level (typ. 2.5V @ 5V) 0 = Normal detection level (typ. 3V @ 5V) PFDEN: Power-fail detection enable bit 1 = Enable power-fail detection 0 = Disable power-fail detection
bit 6
FIGURE 18-1 POWER FAIL DETECTION PROCESSOR
The bit6(PFDEN) of OPTION register activates the PFD Circuit, and bit7(LOWopt) lowers the detection level of the Power Noise. The normal detection level is typically 3V and the lowered detection level is typically 2.5V. Figure 18-2 shows a Power Fail Detection Situations where the detection level is selected by LOWOPT Bit.
Note: The PFD circuit is not implemented on the in circuit emulator, user can not experiment with it. There fore, after final development user program, this function may be experimented on OTP
TNVDD 100nS VDD TIRT PFDR Internal RESET TNVDD 100nS VDD TIRT PFDEN = 1 LOWOPT = 1 PFDR Internal RESET VDD TIRT PFDR Internal RESET POR When VDD falls below approximately 1V level, Power-On Reset may occur. VDD=2.5V VDR VDD=3V VDR
PFDEN = 1 LOWOPT = 0
VDD=3/(2.5)V VDR
VDD VDR PFDEN = 1 LOWOPT = 0/1
FIGURE 18-2 POWER FAIL DETECTION SITUATIONS
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